This is a continuation of U.S. Ser. No. 13/564,019 filed Aug. 1, 2012, now U.S. Pat. No. 8,850,366, the entire disclosure of which is hereby incorporated by reference.
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC design and material have produced generations of ICs where each generation has scaled down to smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing. For these advances to be realized, similar developments in IC processing and manufacturing are needed. For example optical proximity correction (OPC) technique is implemented in a mask fabrication. OPC employs a lithographic model to predict contours of the patterns after the lithography process. A resolution limitation in lithography introduces image distortion in a form of line-end and results in a failure of pattern fidelity correction. It is desired to have improvements in this area.